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?2007 silicon storage technology, inc. s71282-03-eol 7/07 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. intel is a registered trademark of in tel corporation. csf and combomemory are trademarks of silicon storage technology, inc. these specifications are subject to change without notice. eol data sheet features: ? flash organization: 2m x16 or 4m x8 ? dual-bank architecture for concurrent read/write operation ? 32 mbit top sector protection ? 8 mbit + 24 mbit ? sram organization: ? 4 mbit: 256k x16 ? single 2.7-3.3v read and write operations ? superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention ? low power consumption: ? active current: 25 ma (typical) ? standby current: 20 a (typical) ? hardware sector protection (wp#) ? protects 8 kword in the smaller bank by holding wp# low and unprotects by holding wp# high ? hardware reset pin (rst#) ? resets the internal state machine to reading data array ? byte selection for flash (ciof pin) ? selects 8-bit or 16-bit mode ? sector-erase capability ? uniform 2 kword sectors ? flash chip-erase capability ? block-erase capability ? uniform 32 kword blocks ? erase-suspend / erase-resume capabilities ? read access time ? flash: 70 ns ?sram: 70 ns ? security id feature ? sst: 128 bits ? user: 256 bytes ? latched address and data ? fast erase and program (typical): ? sector-erase time: 18 ms ? block-erase time: 18 ms ? chip-erase time: 35 ms ? program time: 7 s ? automatic write timing ? internal v pp generation ? end-of-write detection ? toggle bit ? data# polling ? ready/busy# pin ? cmos i/o compatibility ? jedec standard command set ? packages available ? 56-ball lfbga (8mm x 10mm) ? 62-ball lfbga (8mm x 10mm) ? all non-pb (lead-free) devices are rohs compliant product description the sst34hf3244c combomemory device integrates either a 2m x16 or 4m x8 cmos flash memory bank with a 256k x16 cmos sram memory bank in a multi-chip package (mcp). these devices are fabricated using sst?s proprietary, high-performance cmos superflash technol- ogy incorporating the split-gate cell design and thick-oxide tunneling injector to attain better reliability and manufactur- ability compared with alternate approaches. the sst34hf3244c are ideal for applications such as cellular phones, gps devices, pdas, and other portable electronic devices in a low power and small form factor system. the sst34hf3244c feature dual flash memory bank architecture allowing for concurrent operations between the two flash memory banks and the sram. the devices can read data from either bank while an erase or program operation is in progress in the opposite bank. the two flash memory banks are partitioned into 8 mbit + 24 mbit with top sector protection options for storing boot code, program code, configuration/parameter data and user data. the superflash technology provides fixed erase and pro- gram times, independent of the number of erase/program cycles that have occurred. therefore, the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and program times increase with accumulated erase/pro- gram cycles. the sst34hf3244c devices offer a guaran- teed endurance of 10,000 cycles. data retention is rated at greater than 100 years. with high-performance program operations, the flash memory banks provide a typical pro- gram time of 7 sec. the entire flash memory bank can be erased and programmed word-by-word in typically 4 sec- onds for the sst34hf3244c, when using interface fea- tures such as toggle bit, data# polling, or ry/by# to indicate the completion of program operation. to protect 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c sst34hf32x4x32mb csf + 4/8/16 mb sram (x16) mcp combomemory
2 eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c ?2007 silicon storage technology, inc. s71282-03-eol 7/07 against inadvertent flash write, the sst34hf3244c con- tain on-chip hardware and software data protection schemes. the flash and sram operate as two independent memory banks with respective bank enable signals. the memory bank selection is done by two bank enable signals. the sram bank enable signals, bes1# and bes2, select the sram bank. the flash memory bank enable signal, bef#, has to be used with software data protection (sdp) com- mand sequence when controlli ng the erase and program operations in the flash memory bank. the memory banks are superimposed in the same memory address space where they share common address lines, data lines, we# and oe# which minimize power consumption and area. designed, manufactured, and tested for applications requir- ing low power and small form factor, the sst34hf3244c are offered in both commercial and extended temperatures and a small footprint package to meet board space con- straint requirements. see figure 2 for pin assignments. device operation the sst34hf3244c uses bes1#, bes2 and bef# to control operation of either the flash or the sram memory bank. when bef# is low, the flash bank is activated for read, program or erase operation. when bes1# is low, and bes2 is high the sram is activated for read and write operation. bef# and bes1# cannot be at low level, and bes2 cannot be at high level at the same time. if all bank enable signals are asserted, bus contention will result and the device may suffer permanent damage. all address, data, and control lines are shared by flash and sram memory banks which minimizes power consump- tion and loading. the device goes into standby when bef# and bes1# bank enables are raised to v ihc (logic high) or when bef# is high and bes2 is low. concurrent read/write operation dual bank architecture of sst34hf3244c devices allows the concurrent read/write operation whereby the user can read from one bank while programming or erasing in the other bank. this operation can be used when the user needs to read system code in one bank while updating data in the other bank. see table 3 for dual-bank memory organization. note: for the purposes of this table, write means to perform block-/sector-erase or program operations as applicable to the appropriate bank. flash read operation the read operation of the sst34hf3244c is controlled by bef# and oe#, both have to be low for the system to obtain data from the outputs. bef# is used for device selection. when bef# is high , the chip is deselected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either bef# or oe# is high. refer to the read cycle timing diagram for further details (figure 7). concurrent read/write states flash sram bank 1 bank 2 read write no operation write read no operation write no operation read no operation write read write no operation write no operation write write
eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c 3 ?2007 silicon storage technology, inc. s71282-03-eol 7/07 flash program operation these devices are programmed on a word-by-word or byte-by-byte basis depending on the state of the ciof pin. before programming, one must ensure that the sector being programmed is fully erased. the program operation is accomplished in three steps: 1. software data protection is initiated using the three-byte load sequence. 2. address and data are loaded. during the program operation, the addresses are latched on the fa lling edge of either bef# or we#, whichever occurs last. the data is latched on the rising edge of either bef# or we#, whichever occurs first. 3. the internal program oper ation is initiated after the rising edge of the fourth we# or bef#, which- ever occurs first. the program operation, once ini- tiated, will be completed typically within 7 s. see figures 8 and 9 for we# and bef# controlled pro- gram operation timing diagrams and figure 22 for flow- charts. during the program operation, the only valid reads are data# polling and toggle bit. during the internal pro- gram operation, the host is free to perform additional tasks. any commands issued during an internal program opera- tion are ignored. flash sector- /block -erase operation these devices offer both sector-erase and block-erase operations. these operations allow the system to erase the devices on a sector-by-sector (or block-by-block) basis. the sector architecture is based on a uniform sector size of 2 kword. the block-erase mode is based on a uniform block size of 32 kword. the sector-erase operation is initi- ated by executing a six-byte command sequence with a sector-erase command (50h) and sector address (sa) in the last bus cycle. the block-erase operation is initiated by executing a six-byte command sequence with block-erase command (30h) and block address (ba) in the last bus cycle. the sector or block address is latched on the falling edge of the sixth we# pulse, while the command (30h or 50h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. any commands issued during the block- or sector- erase operation are ignored except erase-suspend and erase-resume. see figures 13 and 14 for timing wave- forms. flash chip-erase operation the sst34hf3244c provide a chip-erase operation, which allows the user to erase all flash sectors/blocks to the ?1? state. this is useful when the device must be quickly erased. the chip-erase operation is initiated by executing a six- byte command sequence with chip-erase command (10h) at address 555h in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or bef#, whichever occurs first. during the erase operation, the only valid read is toggle bits or data# polling. see table 6 for the command sequence, figure 12 for timing diagram, and figure 26 for the flowchart. any commands issued during the chip-erase operation are ignored. when wp# is low, any attempt to chip-erase will be ignored. flash erase-suspend/- resume operations the erase-suspend operation temporarily suspends a sector- or block-erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an erase operation. the operation is executed by issuing a one-byte command sequence with erase-suspend command (b0h). the device automatically enters read mode no more than 10 s after the erase-suspend command had been issued. (t es maximum latency equals 10 s.) valid data can be read from any sector or block that is not suspended from an erase operation. reading at address location within erase- suspended sectors/bl ocks will output dq 2 toggling and dq 6 at ?1?. while in erase-suspend mode, a program operation is allowed except for the sector or block selected for erase-suspend. to resume sector-erase or block- erase operation which has been suspended, the system must issue an erase-resume command. the operation is executed by issuing a one-byte command sequence with erase resume command (30h) at any address in the one- byte sequence.
4 eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c ?2007 silicon storage technology, inc. s71282-03-eol 7/07 flash write operati on status detection the sst34hf3244c provide one hardware and two soft- ware means to detect the completion of a write (program or erase) cycle, in order to optimize the system write cycle time. the hardware detection uses the ready/ busy# (ry/by#) pin. the software detection includes two status bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the ris- ing edge of we#, which initiates the internal program or erase operation. the actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a ready/busy# (ry/ by#), data# polling (dq 7 ) or toggle bit (dq 6 ) read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either dq 7 or dq 6 . in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. ready/busy# (ry/by#) the sst34hf3244c include a ready/busy# (ry/by#) output signal. ry/by# is an open drain output pin that indi- cates whether an erase or program operation is in progress. since ry/by# is an open drain output, it allows several devices to be tied in parallel to v dd via an external pull-up resistor. after the rising edge of the final we# pulse in the command sequence, the ry/by# status is valid. when ry/by# is actively pulled low, it indicates that an erase or program operation is in progress. when ry/by# is high (ready), the devices may be read or left in standby mode. byte/word (ciof) the device includes a ciof pin to control whether the device data i/o pins operate x8 or x16. if the ciof pin is at logic ?1? (v ih ) the device is in x16 data configuration: all data i/0 pins dq 0 -dq 15 are active and controlled by bef# and oe#. if the ciof pin is at logic ?0?, the device is in x8 data config- uration: only data i/o pins dq 0 -dq 7 are active and con- trolled by bef# and oe#. the remaining data pins dq 8 - dq 14 are at hi-z, while pin dq 15 is used as the address input a -1 for the least significant bit of the address bus. flash data# polling (dq 7 ) when the devices are in an internal program operation, any attempt to read dq 7 will produce the complement of the true data. once the program operation is completed, dq 7 will produce true data. during internal erase operation, any attempt to read dq 7 will produce a ?0?. once the internal erase operation is completed, dq 7 will produce a ?1?. the data# polling is valid after the rising edge of fourth we# (or bef#) pulse for program operation. for sector-, block-, or chip-erase, the data# polling is valid after the rising edge of sixth we# (or bef#) pulse. see figure 10 for data# poll- ing (dq 7 ) timing diagram and figure 23 for a flowchart.
eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c 5 ?2007 silicon storage technology, inc. s71282-03-eol 7/07 toggle bits (dq 6 and dq 2 ) during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating ?1?s and ?0?s, i.e., toggling between 1 and 0. when the internal program or erase operation is completed, the dq 6 bit will stop toggling. the device is then ready for the next opera- tion. the toggle bit is valid after the rising edge of the fourth we# (or bef#) pulse for program operations. for sector-, block-, or chip-erase, the toggle bit (dq 6 ) is valid after the rising edge of sixth we# (or bef#) pulse. dq 6 will be set to ?1? if a read operation is attempted on an erase-sus- pended sector/block. if program operation is initiated in a sector/block not selected in erase-suspend mode, dq 6 will toggle. an additional toggle bit is available on dq 2 , which can be used in conjunction with dq 6 to check whether a particular sector is being actively erased or erase-suspended. table 1 shows detailed status bit information. the toggle bit (dq 2 ) is valid after the rising edge of the last we# (or bef#) pulse of a write operation. see figure 11 for toggle bit tim- ing diagram and figure 23 for a flowchart. note: dq 7, dq 6, and dq 2 require a valid address when reading status information. the address must be in the bank where the operation is in progress in order to read the operation sta- tus. if the address is pointing to a different bank (not busy), the device will output array data. data protection the sst34hf3244c provide both hardware and software features to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection: a we# or bef# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when v dd is less than 1.5v. write inhibit mode: forcing oe# low, bef# high, or we# high will inhibit the write oper ation. this prevents inadvert- ent writes during power-up or power-down. hardware block protection the sst34hf3244c provide a hardware block protection which protects the outermost 8 kword/16 kbyte in bank 1. the block is protected when wp# is held low. when wp# is held low and a block-erase command is issued to the protected block, the data in the outermost 8 kword/16 kbyte section will be protected. the rest of the block will be erased. see table 3 for block-protection location. a user can disable block protection by driving wp# high thus allowing erase or program of data into the protected sectors. wp# must be held high prior to issuing the write command and remain stable until after the entire write operation has completed. if wp# is left floating, it is inter- nally held high via a pull-up resistor, and the boot block is unprotected, enabling program and erase operations on that block. hardware reset (rst#) the rst# pin provides a hardware method of resetting the device to read array data. when the rst# pin is held low for at least t rp, any in-progress operat ion will terminate and return to read mode (see figure 19). when no internal program/erase operation is in progress, a minimum period of t rhr is required after rst# is driven high before a valid read can take place (see figure 18). the erase operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity. see figures 18 and 19 for timing diagrams. table 1: write operation status status dq 7 dq 6 dq 2 ry/by# normal operation standard program dq7# toggle no toggle 0 standard erase 0 toggle toggle 0 erase- suspend mode read from erase suspended sector/block 1 1 toggle 1 read from non-erase suspended sector/block data data data 1 program dq7# toggle no toggle 0 t1.1 1282
6 eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c ?2007 silicon storage technology, inc. s71282-03-eol 7/07 software data protection (sdp) the sst34hf3244c provide the jedec standard soft- ware data protection scheme for all data alteration opera- tions, i.e., program and erase. any program operation requires the inclusion of the three-byte sequence. the three-byte load sequence is used to initiate the program operation, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. any erase operation requires the inclusion of six-byte sequence. the sst34hf3244c are shipped with the software data protection permanently enabled. see table 6 for the specific software command codes. during sdp command sequence, invali d commands will abort the device to read mode within t rc. the contents of dq 15 - dq 8 are ?don?t care? during any sdp command sequence. common flash memory interface (cfi) these devices also contain the cfi information to describe the characteristics of the devices. in order to enter the cfi query mode, the system must write the three-byte sequence, same as the software id entry com- mand with 98h (cfi query command) to address bk x 555h in the last byte sequence. in order to enter the cfi query mode, the system can also use the one-byte sequence with bk x 55h on address and 98h on data bus. see figure 16 for cfi entry and read timing diagram. once the device enters the cfi query mode, the system can read cfi data at the addresses given in tables 7 through 9. the system must write the cfi exit command to return to read mode from the cfi query mode. security id the sst34hf3244c devices offer a 136-word security id space. the secure id spac e is divided into two seg- ments?one 128-bit factory programmed segment and one 128-word (256-byte) user-programmed segment. the first segment is programmed and locked at sst with a unique, 128-bit number. the user segment is left un-programmed for the customer to program as desired. to program the user segment of the security id, the user must use the security id program command. end-of-write status is checked by reading the toggle bits. data# polling is not used for security id end-of-write detection. once programming is complete, the sec id should be locked using the user-sec-id-program-lock-out. this disables any future corruption of this space. note that regardless of whether or not the sec id is locked, neither sec id seg- ment can be erased. the secure id space can be queried by executing a three-byte command sequence with query- sec-id command (88h) at address 555h in the last byte sequence. to exit this mode, the exit-sec-id command should be executed. refer to table 6 for more details.
eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c 7 ?2007 silicon storage technology, inc. s71282-03-eol 7/07 product identification the product identification mode identifies the device sst34hf3244c and manufacturer as sst. this mode may be accessed by software operations only. the hard- ware device id read operation, which is typically used by programmers cannot be used on this device because of the shared lines between flash and sram in the multi-chip package. therefore, application of high voltage to pin a 9 may damage this device. users may use the software product identification operation to identify the part (i.e., using the device id) when using multiple manufacturers in the same socket. for details, see tables 5 and 6 for soft- ware operation, figure 15 for the software id entry and read timing diagram and figure 24 for the id entry com- mand sequence flowchart. note: bk = bank address (a 20 -a 18 ) product identification mode exit/ cfi mode exit in order to return to the standard read mode, the software product identification mode must be exited. exit is accom- plished by issuing the software id exit command sequence, which returns the device to the read mode. this command may also be used to reset the device to the read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. please note that the software id exit command is ignored during an internal program or erase operation. see table 6 for software command codes, fig- ure 17 for timing waveform and figure 24 for a flowchart. sram operation with bes1# low, bes2 and bef# high, the sst34hf3244c operates as 25 6k x16cmos sram, with fully static operation requiring no external clocks or timing strobes. the sst34hf3244c sram is mapped into the first 512 kword address space. when bes1#, bef# are high and bes2 is low, all memory banks are deselected and the device enters standby. read and write cycle times are equal. the control signals ubs# and lbs# provide access to the upper data byte and lower data byte. see table 5 for x16 sram read and write data byte control modes of operation. sram read the sram read operation of the sst34hf3244c is con- trolled by oe# and bes1#, both have to be low with we# and bes2 high for the system to obtain data from the out- puts. bes1# and bes2 are used for sram bank selection. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when oe# is high. refer to the read cycle timing diagram, fig- ure 4, for further details. sram write the sram write operation of the sst34hf3244c is con- trolled by we# and bes1#, both have to be low, bes2 must be high for the system to write to the sram. during the word-write operation, the addresses and data are ref- erenced to the rising edge of either bes1#, we#, or the falling edge of bes2 whichever occurs first. the write time is measured from the last falling edge of bes#1 or we# or the rising edge of bes2 to the first rising edge of bes1#, or we# or the falling edge of bes2. refer to the write cycle timing diagrams, figures 5 and 6, for further details. table 2: product identification address data manufacturer?s id bk0000h 00bfh device id sst34hf3244c bk0001h 7353h t2.0 1282
8 eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c ?2007 silicon storage technology, inc. s71282-03-eol 7/07 figure 1: functional block diagram 1282 b1.4 superflash memory (bank 1) i/o buffers superflash memory (bank 2) 4 mbit sram a 20 - a 0 dq 15 /a- 1 - dq 0 control logic rst# bef# wp# lbs# ubs# bes1# bes2 1 oe# 2 we# 2 ry/by# address buffers address buffers notes: 1. for ls package only: we# = wef# and/or wes# oe# = oef# and/or oes#
eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c 9 ?2007 silicon storage technology, inc. s71282-03-eol 7/07 table 3: dual-bank memory organization (1 of 2) sst34hf3244c block block size address range x8 address range x16 bank 1 ba63 8 kw / 16 kb 3fc000h?3fffffh 1fe000h?1fffffh 24 kw / 48 kb 3f0000h?3fbfffh 1f8000h?1fdfffh ba62 32 kw / 64 kb 3e0000h?3effffh 1f0000h?1f7fffh ba61 32 kw / 64 kb 3d0000h?3dffffh 1e8000h?1effffh ba60 32 kw / 64 kb 3c0000h?3cffffh 1e0000h?1e7fffh ba59 32 kw / 64 kb 3b0000h?3bffffh 1d8000h?1dffffh ba58 32 kw / 64 kb 3a0000h?3affffh 1d0000h?1d7fffh ba57 32 kw / 64 kb 390000h?39ffffh 1c8000h?1cffffh ba56 32 kw / 64 kb 380000h?38ffffh 1c0000h?1c7fffh ba55 32 kw / 64 kb 370000h?37ffffh 1b8000h?1bffffh ba54 32 kw / 64 kb 360000h?36ffffh 1b0000h?1b7fffh ba53 32 kw / 64 kb 350000h?35ffffh 1a8000h?1affffh ba52 32 kw / 64 kb 340000h?34ffffh 1a0000h?1a7fffh ba51 32 kw / 64 kb 330000h?33ffffh 198000h?19ffffh ba50 32 kw / 64 kb 320000h?32ffffh 190000h?197fffh ba49 32 kw / 64 kb 310000h?31ffffh 188000h?18ffffh ba48 32 kw / 64 kb 300000h?30ffffh 180000h?187fffh bank 2 ba47 32 kw / 64 kb 2f0000h?2fffffh 178000h?17ffffh ba46 32 kw / 64 kb 2e0000h?2effffh 170000h?177fffh ba45 32 kw / 64 kb 2d0000h?2dffffh 168000h?16ffffh ba44 32 kw / 64 kb 2c0000h?2cffffh 160000h?167fffh ba43 32 kw / 64 kb 2b0000h?2bffffh 158000h?15ffffh ba42 32 kw / 64 kb 2a0000h?2affffh 150000h?157fffh ba41 32 kw / 64 kb 290000h?29ffffh 148000h?14ffffh ba40 32 kw / 64 kb 280000h?28ffffh 140000h?147fffh ba39 32 kw / 64 kb 270000h?27ffffh 138000h?13ffffh ba38 32 kw / 64 kb 260000h?26ffffh 130000h?137fffh ba37 32 kw / 64 kb 250000h?25ffffh 128000h?12ffffh ba36 32 kw / 64 kb 240000h?24ffffh 120000h?127fffh ba35 32 kw / 64 kb 230000h?23ffffh 118000h?11ffffh ba34 32 kw / 64 kb 220000h?22ffffh 110000h?117fffh ba33 32 kw / 64 kb 210000h?21ffffh 108000h?10ffffh ba32 32 kw / 64 kb 200000h?20ffffh 100000h?107fffh ba31 32 kw / 64 kb 1f0000h?1fffffh 0f8000h?0fffffh ba30 32 kw / 64 kb 1e0000h?1effffh 0f0000h?0f7fffh ba29 32 kw / 64 kb 1d0000h?1dffffh 0e8000h?0effffh ba28 32 kw / 64 kb 1c0000h?1cffffh 0e0000h?0e7fffh ba27 32 kw / 64 kb 1b0000h ?1bffffh 0d8000h?0dffffh ba26 32 kw / 64 kb 1a0000h?1affffh 0d0000h?0d7fffh ba25 32 kw / 64 kb 190000h?19ffffh 0c8000h?0cffffh ba24 32 kw / 64 kb 180000h?18ffffh 0c0000h?0c7fffh ba23 32 kw / 64 kb 170000h?17ffffh 0b8000h?0bffffh ba22 32 kw / 64 kb 160000h?16ffffh 0b0000h?0b7fffh
10 eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c ?2007 silicon storage technology, inc. s71282-03-eol 7/07 bank 2 ba21 32 kw / 64 kb 150000h?15ffffh 0a8000h?0affffh ba20 32 kw / 64 kb 140000h?14ffffh 0a0000h?0a7fffh ba19 32 kw / 64 kb 130000h?13ffffh 098000h?09ffffh ba18 32 kw / 64 kb 120000h?12ffffh 090000h?097fffh ba17 32 kw / 64 kb 110000h?11ffffh 088000h?08ffffh ba16 32 kw / 64 kb 100000h?10ffffh 080000h?087fffh ba15 32 kw / 64 kb 0f0000h?0fffffh 078000h?07ffffh ba14 32 kw / 64 kb 0e0000h?0effffh 070000h?077fffh ba13 32 kw / 64 kb 0d0000h?0dffffh 068000h?06ffffh ba12 32 kw / 64 kb 0c0000h?0cffffh 060000h?067fffh ba11 32 kw / 64 kb 0b0000h ?0bffffh 058000h?05ffffh ba10 32 kw / 64 kb 0a0000h?0affffh 050000h?057fffh ba9 32 kw / 64 kb 090000h?09ffffh 048000h?04ffffh ba8 32 kw / 64 kb 080000h?08ffffh 040000h?047fffh ba7 32 kw / 64 kb 070000h?07ffffh 038000h?03ffffh ba6 32 kw / 64 kb 060000h?06ffffh 030000h?037fffh ba5 32 kw / 64 kb 050000h?05ffffh 028000h?02ffffh ba4 32 kw / 64 kb 040000h?04ffffh 020000h?027fffh ba3 32 kw / 64 kb 030000h?03ffffh 018000h?01ffffh ba2 32 kw / 64 kb 020000h?02ffffh 010000h?017fffh ba1 32 kw / 64 kb 010000h?01ffffh 008000h?00ffffh ba0 32 kw / 64 kb 000000h?00ffffh 000000h?007fffh t3.0 1282 table 3: dual-bank memory organization (continued) (2 of 2) sst34hf3244c block block size address range x8 address range x16
eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c 11 ?2007 silicon storage technology, inc. s71282-03-eol 7/07 pin description figure 2: pin assignments for 56-ball lfbga (8mm x 10mm) figure 3: pin assignments for 62-ball lfbga (8mm x 10mm) 1282 56-lfbga p1.1 a11 a8 we# wp# lbs# a7 a15 a12 a19 bes2 rst# ubs# a6 a3 nc a13 a9 a20 ry/by# a18 a5 a2 nc a14 a10 a17 a4 a1 a16 nc dq6 dq1 v ss a0 ciof note* dq13 dq4 dq3 dq9 oe# bef# v ss dq7 dq12 v dds v ddf dq10 dq0 bes1# dq14 dq5 nc dq11 dq2 dq8 a b c d e f g h 8 7 6 5 4 3 2 1 top view (balls facing down) note: f7 = dq 15 /a -1 1282 62-lfbga p2.1 nc nc a20 a16 wef# v sss wp# lbs# a18 nc a11 a8 ry/by# rst# nc ubs# a17 a5 a15 a10 a19 oes# a7 a4 a14 a9 dq11 a6 a0 a13 dq15 dq13 dq12 dq9 a3 bef# a12 wes# dq6 bes2 dq10 dq8 a2 v ssf v ssf dq14 dq4 v dds dq2 dq0 a1 oef# nc dq7 dq5 v ddf dq3 dq1 bes1# nc nc nc a b c d e f g h j k 8 7 6 5 4 3 2 1 top view (balls facing down)
12 eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c ?2007 silicon storage technology, inc. s71282-03-eol 7/07 table 4: pin description symbol pin name functions a ms 1 to a 0 address inputs to provide flash address, a 20 -a 0 . to provide sram address, a mss -a 0 dq 14 -dq 0 data inputs/outputs to output data during read cycles and re ceive input data duri ng write cycles. data is internally latched during a flas h erase/program cycle. the outputs are in tri-state when oe# is high or bes1# is high or bes2 is low and bef# is high. dq 15 /a -1 data input/output and lbs address dq 15 is used as data i/o pin when in x16 mode (ciof = ?1?) a -1 is used as the lbs address pin when in x8 mode (ciof = ?0?) bef# flash memory bank enable to activate the flash memory bank when bef# is low bes1# sram memory bank enable to activate the sram memory bank when bes1# is low bes2 sram memory bank enable to activate the sram memory bank when bes2 is high oef# 2 output enable to gate the data output buffers for flash 2 only oes# 2 output enable to gate the data output buffers for sram 2 only wef# 2 write enable to control the write operations for flash 2 only wes# 2 write enable to control the write operations for sram 2 only oe# output enable to gate the data output buffers we# write enable to control the write operations ciof byte selection for flash when low, select byte mode. when high, select word mode. ubs# upper byte control (sram) to enable dq 15 -dq 8 lbs# lower byte control (sram) to enable dq 7 -dq 0 wp# write protect to protect and unprotect the botto m 8 kword (4 sectors) from erase or program operation rst# reset to reset and return the device to read mode ry/by# ready/busy# to output the status of a program or erase operation ry/by# is a open drain output, so a 10k - 100k pull-up resistor is required to allow ry/by# to transition high indicating the device is ready to read. v ssf 2 ground flash 2 only v sss 2 ground sram 2 only v ss ground v dd f power supply (flash) 2.7-3.3v power supply to flash only v dd s power supply (sram) 2.7-3.3v power supply to sram only nc no connection unconnected pins t4.0 1282 1. a mss = most significant address a mss = a 17 for sst34hf3244c 2. lse package only
eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c 13 ?2007 silicon storage technology, inc. s71282-03-eol 7/07 table 5: operational modes selection for x16 sram mode bef# 1 bes1# 1,2 bes2 1,2 oe# 2,3 we# 2,3 lbs# 2 ubs# 2 dq 15-8 dq 7-0 ciof = v ih ciof = v il full standby v ih v ih x x x x x high-z high-z high-z xv il xxxx output disable v ih v il v ih v ih v ih x x high-z high-z high-z v il v ih xxv ih v ih v il v ih xv ih v ih x x high-z high-z high-z xv il flash read v il v ih xv il v ih xxd out d out dq 14-8 = high-z dq 15 = a -1 xv il flash write v il v ih x v ih v il xxd in d in dq 14-8 = high-z dq 15 = a -1 xv il flash erase v il v ih xv ih v il xx x x x xv il sram read v ih v il v ih v il v ih v il v il d out d out d out v ih v il high-z d out d out v il v ih d out high-z high-z sram write v ih v il v ih xv il v il v il d in d in d in v ih v il high-z d in d in v il v ih d in high-z high-z product identification 4 v il v ih v il v il v ih x x manufacturer?s id 5 device id 5 t5.1 1282 1. do not apply bef# = v il , bes1# = v il and bes2 = v ih at the same time 2. x can be v il or v ih, but no other value. 3. oe# = oef# and oes# we# = wef# and wes# for lse package only 4. software mode only 5. with a 19 -a 18 = v il; sst manufacturer?s id = bfh, is read with a 0 =0, sst34hf3244c device id = 7351h, is read with a 0 =1
14 eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c ?2007 silicon storage technology, inc. s71282-03-eol 7/07 table 6: software command sequence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 word-program 555h aah 2aah 55h 555h a0h wa 3 data sector-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa x 4 50h block-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h ba x 4 30h chip-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h erase-suspend xxxxh b0h erase-resume xxxxh 30h query sec id 5 555h aah 2aah 55h 555h 88h user-security-id- program 555h aah 2aah 55h 555h a5h siwa 6 data user-security-id- program-lock-out 7 555h aah 2aah 55h 555h 85h xxh 0000h software id entry 8 555h aah 2aah 55h bk x 9 555h 90h cfi query entry 555h aah 2aah 55h bk x 4 555h 98h cfi query entry bk x 4 55h 98h software id exit/ cfi exit/ sec id exit 10,11 555h aah 2aah 55h 555h f0h software id exit/ cfi exit/ sec id exit 10,11 xxh f0h t6.1 1282 1. address format a 10- a 0 (hex), addresses a 20 -a 11 can be v il or v ih , but no other value, for the command sequence when in x16 mode. when in x8 mode, addresses a 20 -a 12, address a -1 and dq 14 -dq 8 can be v il or v ih , but no other value, for the command sequence. 2. dq 15 -dq 8 can be v il or v ih , but no other value, for the command sequence 3. wa = program word/byte address 4. sa x for sector-erase; uses a 20 -a 11 address lines ba x for block-erase; uses a 20 -a 15 address lines 5. for sst34hf3244c the security id address range is: (x16 mode) = 000000h to 000087h, (x8 mode) = 000000h to 00010fh sst id is read at address range (x16 m ode) = 000000h to 000007h (x8 mode) = 000000h to 00000fh user id is read at address range (x16 m ode) = 000008h to 000087h (x8 mode) = 000010h to 00010fh lock status is read at address 0000ffh (x16) or 0001ffh (x8). unlocked: dq3 = 1 / locked: dq3 = 0. 6. siwa = user security id program word/byte address for sst34hf3244c, valid address range is (x16 mode) = 000008h-000087h (x8 mode) = 000010h-00010fh. all 4 cycles of user security id program and program lock- out must be completed before going back to read-array mode. 7. the user-security-id-program-lock-out comm and must be executed in x16 mode. (ciof = v ih ) 8. the device does not remain in software product identification mode if powered down. 9. a 19 and a 18 = v il 10. both software id exit operations are equivalent 11. iif users never lock after programming, user sec id can be pr ogrammed over the previously unpr ogrammed bits (data=1) using t he user sec id mode again (the programmed ?0? bits cannot be reversed to ?1?).
eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c 15 ?2007 silicon storage technology, inc. s71282-03-eol 7/07 table 7: cfi query identification string 1 address x16 mode address x8 mode data 2 description 10h 20h 0051h query unique ascii string ?qry? 11h 22h 0052h 12h 24h 0059h 13h 26h 0002h primary oem command set 14h 28h 0000h 15h 2ah 0000h address for primary extended table 16h 2ch 0000h 17h 2eh 0000h alternate oem command set (00h = none exists) 18h 30h 0000h 19h 32h 0000h address for alternate oem extended table (00h = none exits) 1ah 34h 0000h t7.1 1282 1. refer to cfi publication 100 for more details. 2. in x8 mode, only the lower byte of data is output. table 8: system interface information address x16 mode address x8 mode data 1 1. in x8 mode, only the lower byte of data is output. description 1bh 36h 0027h v dd min (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1ch 38h 0036h v dd max (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1dh 3ah 0000h v pp min (00h = no v pp pin) 1eh 3ch 0000h v pp max (00h = no v pp pin) 1fh 3eh 0004h typical time out for program 2 n s (2 4 = 16 s) 20h 40h 0000h typical time out for min size buffer program 2 n s (00h = not supported) 21h 42h 0004h typical time out for individual sector/block-erase 2 n ms (2 4 = 16 ms) 22h 44h 0006h typical time out for chip-erase 2 n ms (2 6 = 64 ms) 23h 46h 0001h maximum time out for program 2 n times typical (2 1 x 2 4 = 32 s) 24h 48h 0000h maximum time out for buffer program 2 n times typical 25h 4ah 0001h maximum time out for individual sector-/block-erase 2 n times typical (2 1 x 2 4 = 32 ms) 26h 4ch 0001h maximum time out for chip-erase 2 n times typical (2 1 x 2 6 = 128 ms) t8.0 1282
16 eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c ?2007 silicon storage technology, inc. s71282-03-eol 7/07 table 9: device geometry information address x16 mode address x8 mode data 1 description 27h 4eh 0016h device size = 2 n bytes (16h = 22; 2 22 = 4 mbyte) 28h 50h 0002h flash device interface description; 0002h = x8/x16 asynchronous interface 29h 52h 0000h 2ah 54h 0000h maximum number of bytes in multi-byte write = 2 n (00h = not supported) 2bh 56h 0000h 2ch 58h 0002h number of erase sector /block sizes supported by device 2dh 5ah 003fh block information (y + 1 = number of blocks; z x 256b = block size) 2eh 5ch 0000h y = 63 + 1 = 64 blocks (003fh = 63) 2fh 5eh 0000h 30h 60h 0001h z = 256 x 256 bytes = 64 kbyte/block (0100h = 256) 31h 62h 00ffh sector information (y + 1 = numb er of sectors; z x 256b = sector size) 32h 64h 0003h y = 1023 + 1 = 1024 sectors (03ffh = 1023) 33h 66h 0010h 34h 68h 0000h z = 16 x 256 bytes = 4 kbyte/sector (0010h = 16) t9.2 1282 1. in x8 mode, only the lower byte of data is output.
eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c 17 ?2007 silicon storage technology, inc. s71282-03-eol 7/07 absolute maximum stress ratings (applied conditions greater than t hose listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. exposu re to absolute maximum stress rating co nditions may affect device reliability.) operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20c to +85c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +125c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v to v dd 1 +0.3v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0v to v dd 1 +1.0v package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount solder reflow temperature 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds output short circuit current 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. v dd = v ddf and v dds 2. excluding certain with-pb 32-plcc units, all packages are 260 c capable in both non-pb and with-pb solder versions. certain with-pb 32-plcc package types are capable of 240 c for 10 seconds; please consult the factory for the latest information. 3. outputs shorted for no more than one second. no more than one output shorted at a time. operating range range ambient temp v dd extended -20c to +85c 2.7-3.3v ac conditions of test input rise/fall time . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . c l = 30 pf see figures 20 and 21
18 eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c ?2007 silicon storage technology, inc. s71282-03-eol 7/07 table 10: dc operating characteristics (v dd = v ddf and v dds = 2.7-3.3v) symbol parameter limits test conditions min max units i dd 1 active v dd current address input = v ilt /v iht, at f=5 mhz, v dd =v dd max, all dqs open read oe#=v il , we#=v ih flash 35 ma bef#=v il , bes1#=v ih , or bes2=v il sram 30 ma bef#=v ih , bes1#=v il , bes2=v ih concurrent operation 60 ma bef#=v ih , bes1#=v il , bes2=v ih write 2 we#=v il flash 40 ma bef#=v il , bes1#=v ih , or bes2=v il , oe#=v ih sram 30 ma bef#=v ih , bes1#=v il , bes2=v ih i sb standby v dd current 30 a v dd = v dd max, bef#=bes1#=v ihc , bes2=v ilc i rt reset v dd current 30 a rst#=gnd i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i liw input leakage current on wp# pin and rst# pin 10 a wp#=gnd to v dd , v dd =v dd max rst#=gnd to v dd , v dd =v dd max i lo output leakage current 10 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ilc input low voltage (cmos) 0.3 v v dd =v dd max v ih input high voltage 0.7 v dd vv dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v v dd =v dd max v olf flash output low voltage 0.2 v i ol =100 a, v dd =v dd min v ohf flash output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min v ols sram output low voltage 0.4 v iol =1 ma, v dd =v dd min v ohs sram output high voltage 2.2 v ioh =-500 a, v dd =v dd min t10.0 1282 1. address input = v ilt /v iht, v dd =v dd max (see figure 20) 2. i dd active while erase or program is in progress.
eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c 19 ?2007 silicon storage technology, inc. s71282-03-eol 7/07 table 11: recommended system power-up timings symbol parameter minimum units t pu-read 1 power-up to read operation 100 s t pu-write 1 power-up to write operation 100 s t11.0 1282 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. table 12: capacitance (t a = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. i/o pin capacitance v i/o = 0v 20 pf c in 1 input capacitance v in = 0v 16 pf t12.0 1282 table 13: flash reliability characteristics symbol parameter minimum spec ification units test method n end 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t13.0 1282
20 eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c ?2007 silicon storage technology, inc. s71282-03-eol 7/07 ac characteristics table 14: sram read cycle timing parameters min max units t rcs read cycle time 70 ns t aas address access time 70 ns t bes bank enable access time 70 ns t oes output enable access time 35 ns t byes ubs#, lbs# access time 70 ns t blzs 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. bes# to active output 0 ns t olzs 1 output enable to active output 0 ns t bylzs 1 ubs#, lbs# to active output 0 ns t bhzs 1 bes# to high-z output 25 ns t ohzs 1 output disable to high-z output 25 ns t byhzs 1 ubs#, lbs# to high-z output 35 ns t ohs output hold from address change 10 ns t14.0 1282 table 15: sram write cycle timing parameters symbol parameter min max units t wcs write cycle time 70 ns t bws bank enable to end-of-write 60 ns t aws address valid to end-of-write 60 ns t asts address set-up time 0 ns t wps write pulse width 60 ns t wrs write recovery time 0 ns t byws ubs#, lbs# to end-of-write 60 ns t odws output disable from we# low 30 ns t oews output enable from we# high 0 ns t dss data set-up time 30 ns t dhs data hold from write time 0 ns t15.0 1282
eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c 21 ?2007 silicon storage technology, inc. s71282-03-eol 7/07 table 16: flash read cycle timing parameters v dd = 2.7-3.3v symbol parameter min max units t rc read cycle time 70 ns t ce chip enable access time 70 ns t aa address access time 70 ns t oe output enable access time 35 ns t clz 1 bef# low to active output 0 ns t olz 1 oe# low to active output 0 ns t chz 1 bef# high to high-z output 16 ns t ohz 1 oe# high to high-z output 16 ns t oh 1 output hold from address change 0 ns t rp 1 rst# pulse width 500 ns t rhr 1 rst# high before read 50 ns t ry 1,2 rst# pin low to read 20 s t16.0 1282 1. this parameter is measured only for init ial qualification and after the design or pr ocess change that could affect this param eter. 2. this parameter applies to sector-erase, block-erase and pr ogram operations. this parameter does not apply to chip-erase. table 17: flash program/erase cycle timing parameters symbol parameter min max units t bp program time 10 s t as address setup time 0 ns t ah address hold time 40 ns t cs we# and bef# setup time 0 ns t ch we# and bef# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp bef# pulse width 40 ns t wp we# pulse width 40 ns t wph 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. we# pulse width high 30 ns t cph 1 bef# pulse width high 30 ns t ds data setup time 30 ns t dh 1 data hold time 0 ns t ida 1 software id access and exit time 150 ns t es erase-suspend latency 10 s t by 1,2 2. this parameter applies to sector-erase, block-erase, and program operations. this parameter does not apply to chip-erase operations. ry/by# delay time 90 ns t br 1 bus recovery time 1s t se sector-erase 25 ms t be block-erase 25 ms t sce chip-erase 50 ms t17.1 1282
22 eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c ?2007 silicon storage technology, inc. s71282-03-eol 7/07 figure 4: sram read cycle timing diagram addresses a mss-0 dq 15-0 ubs#, lbs# oe# bes1# bes2 t rcs t aas t bes t oes t blzs t olzs t byes t bylzs t byhzs data valid t ohzs t bhzs t ohs 1282 f01.0 t bes note: a mss = most significant address a mss = a 17 for sst34hf3244c
eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c 23 ?2007 silicon storage technology, inc. s71282-03-eol 7/07 figure 5: sram write cycle timing diagram (we# controlled) addresses a mss 3 -0 bes1# bes2 we# ubs#, lbs# t wps t wrs t wcs t asts t bws t bws t byws t odws t oews t dss t dhs 1282 f02.0 note 2 dq 15-8, dq 7-0 valid data in note 2 t aws note: 1. if oe# is high during the write cycle, the outputs will remain at high impedance. 2. if bes1# goes low or bes2 goes high coincident with or afte r we# goes low, the output will remain at high impedance. if bes1# goes high or bes2 goes low coincident with or before we# goes high, the output will remain at high impedance. because d in signals may be in the output state at this time, input signals of reverse polarity must not be applied. 3. a mss = most significant sram address a mss = a 17 for sst34hf3244c
24 eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c ?2007 silicon storage technology, inc. s71282-03-eol 7/07 figure 6: sram write cycle timing diagram (ubs#, lbs# controlled) addresses a mss 3 -0 we# bes1# bes2 t bws t bws t aws t wcs t wps t wrs t asts t byws dq 15-8, dq 7-0 valid data in t dss t dhs ubs#, lbs# 1282 f03.0 note 2 note 2 note: 1. if oe# is high during the write cycle, the outputs will remain at high impedance. 2. because d in signals may be in the output state at this time, i nput signals of reverse polarity must not be applied. 3. a mss = most significant sram address a mss = a 17 for sst34hf3244c
eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c 25 ?2007 silicon storage technology, inc. s71282-03-eol 7/07 figure 7: flash read cycle timing diagram for word mode (for byte mode a -1 = address input) figure 8: flash we# controlled program cycle timing diagram for word mode (for byte mode a -1 = address input) 1282 f04.0 address a 20-0 dq 15-0 we# oe# bef# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz 1282 f05.0 address a 20-0 dq 15-0 t dh t wph t ds t wp t ah t as t ch t cs t by bef# ry/by# 555 2aa 555 addr xxaa xx55 xxa0 data word (addr/data) oe# we# t br t bp note: x can be v il or v ih , but no other value. valid
26 eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c ?2007 silicon storage technology, inc. s71282-03-eol 7/07 figure 9: flash bef# controlled program cycle timing diagram for word mode (for byte mode a -1 = address input) figure 10: flash data# polling timing diagram for word mode (for byte mode a -1 = address input) valid 1335 f06.0 address a 20-0 dq 15-0 t dh t cph t ds t cp t ah t as t ch t cs ? we# 555 2aa 555 addr xxaa xx55 xxa0 data word (addr/data) oe# bef# t bp t by ry/by# t br note: x can be v il or v ih , but no other value. 1282 f07.0 address a 20-0 dq 7 data data# data# data we# oe# bef# t oeh t oe t ce t oes ry/by# t by
eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c 27 ?2007 silicon storage technology, inc. s71282-03-eol 7/07 figure 11: flash toggle bit timing diagram for word mode (for byte mode a -1 = don?t care) figure 12: flash we# controlled chip-erase timing diagram for word mode (for byte mode a -1 = don?t care) 1282 f08.0 address a 20-0 dq 6 we# oe# bef# t oe t oeh t ce two read cycles with same outputs valid data t br valid t br 1282 f09.0 address a 20-0 dq 15-0 we# 555 2aa 2aa 555 555 xx55 xx10 xx55 xxaa xx80 xxaa 555 oe# bef# six-byte code for chip-erase t sce t wp t by ry/by# note: this device also supports bef# controlled chip-erase operation. the we# and bef# signals are interchangeable as long as minimum timings are met. (see table 17.) x can be v il or v ih, but no other value.
28 eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c ?2007 silicon storage technology, inc. s71282-03-eol 7/07 figure 13: flash we# controlled block-erase timing diagram for word mode (for byte mode a -1 = don?t care) figure 14: flash we# controlled sector-erase timing diagram for word mode (for byte mode a -1 = don?t care) 1282 f10.0 address a 20-0 dq 15-0 we# 555 2aa 2aa 555 555 xx55 xx30 xx55 xxaa xx80 xxaa ba x oe# bef# six-byte code for block-erase t wp t by ry/by# valid t br t be note: this device also supports bef# controlled block-erase operation. the we# and bef# signals are interchangeable as long as minimum timings are met. (see table 17.) ba x = block address x can be v il or v ih, but no other value. 1282 f11.0 address a 20-0 dq 15-0 we# 555 2aa 2aa 555 555 xx55 xx50 xx55 xxaa xx80 xxaa sa x oe# bef# six-byte code for sector-erase t wp t by ry/by# valid t br t se note: this device also supports bef# controlled sector-erase operation. the we# and bef# signals are interchangeable as long as minimum timings are met. (see table 17.) sa x = sector address x can be v il or v ih, but no other value.
eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c 29 ?2007 silicon storage technology, inc. s71282-03-eol 7/07 figure 15: flash software id entry and read (for byte mode a -1 = 0) figure 16: cfi entry and read 1282 f12.0 address a 20-0 t ida dq 15-0 we# 555 2aa 555 0000 0001 oe# bef# three-byte sequence for software id entry t wp t wph t aa 00bf device id xx55 xxaa xx90 note: x can be v il or v ih, but no other value. device id =7353h for sst34hf3244c 1282 f22.0 addresses t ida dq 15-0 we# 555 2aa 555 oe# ce# three-byte sequence for cfi query entry t wp t wph t aa xx55 xxaa xx98 note: x can be v il or v ih, but no other value.
30 eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c ?2007 silicon storage technology, inc. s71282-03-eol 7/07 figure 17: software id exit/cfi exit 1335 f23.0 addresses dq 15-0 t ida t wp t wph we# 555 2aa 555 three-byte sequence for software id exit and reset oe# ce# xxaa xx55 xxf0 note: x can be v il or v ih , but no other value.
eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c 31 ?2007 silicon storage technology, inc. s71282-03-eol 7/07 figure 18: rst# timing (when no inte rnal operation is in progress) figure 19: rst# timing (during sector- or block-erase operation) 1282 f13.0 ry/by# 0v rst# bef#/oe# t rp t rhr 1282 f14.0 ry/by# bef# oe# t rp t ry t br rst#
32 eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c ?2007 silicon storage technology, inc. s71282-03-eol 7/07 figure 20: ac input/output reference waveforms figure 21: a test load example 1282 f15.0 reference points output input? v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 1282 f16.0 to tester to dut c l
eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c 33 ?2007 silicon storage technology, inc. s71282-03-eol 7/07 figure 22: program algorithm 1282 f17.0 start load data: xxaah address: 555h load data: xx55h address: 2aah load data: xxa0h address: 555h load address/data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed note: x can be v il or v ih , but no other value.
34 eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c ?2007 silicon storage technology, inc. s71282-03-eol 7/07 figure 23: wait options 1282 f18.0 wait t bp , t sce, t se or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same byte/word data# polling program/erase completed program/erase completed read byte/word is dq 7 = true data? read dq 7 program/erase initiated program/erase initiated
eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c 35 ?2007 silicon storage technology, inc. s71282-03-eol 7/07 figure 24: software product id command flowcharts 1282 f19.1 load data: xxaah address: 555h software product id entry command sequence load data: xx55h address: 2aah load data: xx90h address: 555h wait t ida read software id load data: xxaah address: 555h software id exit/ cfi exit command sequence load data: xx55h address: 2aah load data: xxf0h address: 555h wait t ida return to normal operation note: x can be v il or v ih, but no other value. load data: xxaah address: 555h cfi query entry command sequence load data: xx55h address: 2aah load data: xx98h address: 555h wait t ida read cfi data
36 eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c ?2007 silicon storage technology, inc. s71282-03-eol 7/07 figure 25: software sec id command flowcharts 1282 f20.0 sec id exit command sequence load data: xxf0h address: xxh return to normal operation wait t ida x can be v il or v ih, but no other value load data: xxaah address: 555h sec id query entry command sequence load data: xx55h address: 2aah load data: xx88h address: 555h wait t ida read sec id load data: xxaah address: 555h load data: xx55h address: 2aah load data: xxf0h address: 555h wait t ida return to normal operation
eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c 37 ?2007 silicon storage technology, inc. s71282-03-eol 7/07 figure 26: erase command sequence 1282 f21.0 load data: xxaah address: 555h chip-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx10h address: 555h load data: xxaah address: 555h wait t sce chip erased to ffffh load data: xxaah address: 555h sector-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx50h address: sa x load data: xxaah address: 555h wait t se sector erased to ffffh load data: xxaah address: 555h block-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx30h address: ba x load data: xxaah address: 555h wait t be block erased to ffffh note: x can be v il or v ih, but no other value.
38 eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c ?2007 silicon storage technology, inc. s71282-03-eol 7/07 product ordering information valid combinations for sst34hf3244c sst34hf3244c-70-4e-l1pe SST34HF3244C-70-4E-LSE note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid combinat ions and to determine availability of new combinations. environmental attribute e 1 = non-pb package modifier p= 56 balls s = 62 balls package type l1 = lfbga (8mm x 10mm x 1.4mm, 0.45mm ball size) l = lfbga (8mm x 10mm x 1.4mm, 0.40mm ball size) temperature range e= extended = -20c to +85c minimum endurance 4 =10,000 cycles read access speed 70 = 70 ns version c = x16 mbit sram bank split and top boot block protection 4 = 8 mbit + 24 mbit sram density 4 = 4 mbit flash density 32 = 32 mbit voltage h = 2.7-3.3v product series 34 = concurrent superflash + sram combomemory 1. environmental suffix ?e? denotes non-pb solder. sst non-pb solder devices are ?rohs compliant?. device speed suffix1 suffix2 sst34 h f 3244c -70 -x x -xx s e
eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c 39 ?2007 silicon storage technology, inc. s71282-03-eol 7/07 packaging diagrams figure 27: 56-ball low-profile, fine-pitch ball grid array (lfbga) 8mm x 10mm sst package code: l1p h g f e d c b a a b c d e f g h side view 8 7 6 5 4 3 2 1 seating plane 0.35 0.05 1.30 0.10 0.12 0.45 0.05 (56x) 0.80 5.60 0.80 5.60 56-lfbga-l1p-8x10-450mic-4 note: 1. although many dimensions are similar to those of jedec publication 95, mo-210, this specific package is not registere d. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.12 mm 4. ball opening size is 0.38 mm ( 0.05 mm) 8 7 6 5 4 3 2 1 1mm a1 corner bottom view top view 8.00 0.20 a1 corner 10.00 0.20
40 eol data sheet 32 mbit concurrent superflash + 4 mbit sram combomemory sst34hf3244c ?2007 silicon storage technology, inc. s71282-03-eol 7/07 figure 28: 62-ball low-profile, fine-pitch ball grid array (lfbga) 8mm x 10mm sst package code: ls table 18: revision history number description date 00 ? initial release aug 2005 01 ? added sst34hf3282-70-4e-lse part number jun 2006 02 ? removed psram references to s71335 aug 2006 03 ? end-of-life data sheet for all valid combinations in s71282 jun 2007 a1 corner k j h g f e d c b a a b c d e f g h j k bottom view top view 8 7 6 5 4 3 2 1 8.00 0.20 0.40 0.05 (62x) a1 corner 10.00 0.20 0.80 5.60 0.80 7.20 62-lfbga-ls-8x10-400mic-4 note: 1. although many dimensions are similar to those of jedec publication 95, mo-210, this specific package is not registere d. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.12 mm 4. ball opening size is 0.32 mm ( 0.05 mm) 8 7 6 5 4 3 2 1 1mm side view seating plane 0.32 0.05 1.30 0.10 0.12 silicon storage technology, inc. ? 1171 sonora court ? sunnyvale, ca 94086 ? telephone 408-735-9110 ? fax 408-735-9036 www.superflash.com or www.sst.com

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